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mosel vitelic 1 V62C31162048 128k x 16 static ram preliminary information V62C31162048 rev. 0.3 february 1999 features n high-speed: 35, 70 ns n ultra low dc operating current of 4ma (max.) ttl standby: 1 ma (max.) cmos standby: 15 m a (max.) n fully static operation n all inputs and outputs directly ttl compatible n three state outputs n ultra low data retention current (v cc = 2v) n extended operating voltage: 2.7v ?3.6v n packages 44-pin tsop (standard) 44-pin 400 mil soj description the V62C31162048 is a 2,097,152-bit static random-access memory organized as 131,072 words by 16 bits. it is built with mosel vitelic? high performance cmos process. inputs and three-state outputs are ttl compatible and allow for direct interfacing with common system bus structures. device usage chart operating temperature range package outline access time (ns) power temperature mark t k 35 70 l ll 0 c to 70 c blank ?0 c to +85 c i functional block diagram row decoder 1024 x 1024 memory array input data circuit column i/o column decoder control circuit v cc gnd a 0 31162048-01 a 15 a 16 a 11 a 7 i/o 0 i/o 15 lbe oe we ube a 8 a 10 a 12 a 14 ce
2 V62C31162048 rev. 0.3 february 1999 mosel vitelic V62C31162048 pin descriptions a 0 ? 16 address inputs these 16 address inputs select one of the 128k x 16 bit segments in the ram. ce , ce2* chip enable inputs ce is active low. ce2 is active high. it must be active to read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. the i/o pins will be in the high-impedance state when deselected. oe output enable input the output enable input is active low. when oe is low with ce low and we high, data will be pre- sented on the i/o pins. the i/o pins will be in the high impedance state when oe is high. ube , leb byte enable active low inputs. these inputs are used to enable the upper or lower data byte. we write enable input the write enable input is active low and controls read and write operations. with the chip enabled, when we is high and oe is low, output data will be present at the i/o pins; when we is low and oe is high, the data present on the i/o pins will be written into the selected memory locations. i/o 0 ?/o 15 data input and data output ports these 16 bidirectional ports are used to read data from and write data into the ram. v cc power supply gnd ground pin configurations (top view) 44-pin soj 44-pin tsop-ii (standard) 144 31162048-02 2 43 3 42 441 540 6 39 7 38 837 936 10 35 11 34 12 33 13 32 14 31 15 30 16 29 a 3 a 4 a 2 a 1 a 0 ce1 i/o 0 i/o 1 i/o 2 i/o 3 v cc gnd i/o 4 i/o 5 i/o 6 i/o 7 we a 6 a 7 oe ube lbe i/o 15 i/o 14 i/o 13 i/o 12 v cc gnd i/o 11 i/o 10 i/o 9 i/o 8 17 28 a 15 ce2/nc* 18 27 a 14 a 8 19 26 a 13 a 9 20 25 a 12 a 10 21 24 a 16 a 11 22 23 nc a 5 a4 a3 a2 a1 a0 ce i/o0 i/o1 i/o2 i/o3 vcc gnd i/o4 i/o5 i/o6 i/o7 we a15 a14 a13 a12 a16 a5 a6 a7 oe ube lbe i/o15 i/o14 i/o13 i/o12 gnd vcc i/o11 i/o10 i/o9 i/o8 ce2/nc* a8 a9 a10 a11 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 31162048-03 *this pin can be left floating. an internal pull up keeps this pin asserted.
mosel vitelic V62C31162048 3 V62C31162048 rev. 0.3 february 1999 part number information absolute maximum ratings (1) note: 1. stresses greater than those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. symbol parameter commercial industrial units v cc supply voltage -0.5 to v cc + 0.5 -0.5 to v cc + 0.5 v v n input voltage -0.5 to v cc + 0.5 -0.5 to v cc + 0.5 v v dq input/output voltage applied v cc + 0.3 v cc + 0.3 v t bias temperature under bias -10 to +125 -65 to +135 c t stg storage temperature -55 to +125 -65 to +150 c sram family c = cmos process 62 = standard 31 = 2.7v ?3.6v operating voltage 2048k organization pkg speed 31162048-04 62 c 16 31 1024 mosel-vitelic manufactured v 16 = 16-bit 35 ns 70 ns temp. blank = 0 c to 70 c i = -40 c to +85 c t = tsop standard k = 400 mil soj density pwr. l = low power ll = double low power capacitance* t a = 25 c, f = 1.0mhz note: 1. this parameter is guaranteed and not tested. symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v i/o = 0v 8 pf truth table note: x = don? care, l = low, h = high mode ce oe we ube lbe i/o 8-15 operation i/o 0-7 operation standby h x x x x high z high z output disable l x x h h high z high z output disable l h h x x high z high z read l l h l l d out d out read l l h l h d out high z read l l h h l high z d out write l x l l l d in d in write l x l l h d in high z write l x l h l high z d in
4 V62C31162048 rev. 0.3 february 1999 mosel vitelic V62C31162048 dc electrical characteristics (over all temperature ranges, v cc = 2.7v ?3.6v) notes: 1. these are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. v il (min.) = -3.0v for pulse width < 20ns. 3. f max = 1/t rc . 4. maximum values. symbol parameter test conditions min. typ. max. units v il input low voltage (1,2) -0.3 0.4 v v ih input high voltage (1) 2.2 v cc + 0.3 v i il input leakage current v cc = max, v in = 0v to v cc -1 1 m a i ol output leakage current v cc = max, ce = v ih , v out = 0v to v cc -1 1 m a v ol output low voltage v cc = min, i ol = 2.1ma 0.4 v v oh output high voltage v cc = min, i oh = -1ma 2.4 v symbol parameter power com. (4) ind. units i cc operating power supply current, ce = v il , output open, v cc = max., f = 0 l56ma ll 4 5 i cc1 average operating current, ce 1 = v il , output open, v cc = max., f = f max (3) 50 60 ma i sb ttl standby current ce 3 v ih , v cc = max., f = f max (3) l23ma ll 1 2 i sb1 cmos standby current, ce 3 v cc ?0.2v, v in 3 v cc ?0.2v or v in 0.2v, v cc = max., f = 0 l3040 m a ll 15 20 ac test conditions ac test loads and waveforms key to switching waveforms input pulse levels 0 to 3v input rise and fall times 5 ns timing reference levels 1.5v output load see below 3v 1800 990 * includes scope and jig capacitance i/o pins c l = 30 pf* 31162048-05 waveform inputs outputs must be steady will be steady may change from h to l will be changing from h to l may change from l to h will be changing from l to h don't care: any change permitted changing: s tat e unknown does not apply center line is high impedance ?ff state
mosel vitelic V62C31162048 5 V62C31162048 rev. 0.3 february 1999 data retention characteristics notes: 1. t rc = read cycle time 2. t a = +25 c. low v cc data retention waveform (ce controlled) symbol parameter power min. typ. (2) max. units v dr v cc for data retention ce 3 v cc ?0.2v, v in 3 v cc ?0.2v, or v in 0.2v 2.0 3.6 v i ccdr data retention current ce 3 v dr ?.2v, v in 3 v cc ?0.2v, or v in 0.2v com? l 1 50 m a ll 0.5 10 ind. l 100 ll 15 t cdr chip deselect to data retention time 0 ns t r operation recovery time (see retention waveform) t rc (1) ns v cc 31162048-06 data retention mode ce 3 v cc ?0.2v ce 2.2v 2.2v 4.5v t cdr t r v dr 3 2v 4.5v
6 V62C31162048 rev. 0.3 february 1999 mosel vitelic V62C31162048 ac electrical characteristics (over all temperature ranges) read cycle write cycle parameter name parameter -35 -70 unit min. max. min. max. t rc read cycle time 35 70 ns t aa address access time 35 70 ns t acs chip enable access time 35 70 ns t ba ube , lbe access time 10 35 ns t oe output enable to output valid 10 35 ns t clz chip enable to output in low z 3 10 ns t blz ube , lbe to output in low z 3 10 ns t olz output enable to output in low z 5?ns t chz chip disable to output in high z 0 10 0 25 ns t ohz output disable to output in high z 0 10 0 25 ns t bhz ube , lbe to output in high z 0 10 0 15 ns t oh output hold from address change 3?ns parameter name parameter -35 -70 unit min. max. min. max. t wc write cycle time 35 70 ns t cw chip enable to end of write 25 60 ns t as address setup time 0?ns t aw address valid to end of write 25 60 ns t wp write pulse width 25 50 ns t wr write recovery time 0?ns t whz write to output high-z 0 10 0 25 ns t wlz write to output low z 3?ns t dw data setup to end of write 20 30 ns t dh data hold from end of write 0?ns t bw ube , lbe to end of write 20 30 ns
mosel vitelic V62C31162048 7 V62C31162048 rev. 0.3 february 1999 switching waveforms (read cycle) read cycle 1 (1, 2) read cycle 2 (1, 2, 4, 6) read cycle 3 (1, 3, 4, 6) notes: 1. we = v ih . 2. ce 1 = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. transition is measured 500mv from steady state with c l = 5pf. this parameter is guaranteed and not 100% tested. 6. ube = v il , lbe = v il . address 31162048-07 oe i/o ube, lbe t rc t aa t oe t bhz t olz t blz t ba t ohz (5) address i/o 31162048-08 t rc t aa t oh t oh address 31162048-09 i/o ce t acs t clz (5) t chz (5)
8 V62C31162048 rev. 0.3 february 1999 mosel vitelic V62C31162048 switching waveforms (write cycle) write cycle 1 (we controlled) (4) write cycle 2 (ce controlled) (4) notes: 1. the internal write time of the memory is defined by the overlap of ce active and we low. all signals must be active to initiate and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. t wr is measured from the earlier of ce or we going high. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the outputs must not be a pplied. 4. oe = v il or v ih . however it is recommended to keep oe at v ih during write cycle to avoid bus contention. 5. if ce is low during this period, i/o pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 6. t cw is measured from ce going low to the end of write. address output input ce we 31162048-10 t wc t cw (6) t dw t dh t aw t wr (2) t whz (3) t wp (1) t as ube, lbe t bw address output input ce we ube, lbe 31162048 -11 t wc t dw t dh t aw t wr (2) hi-z t as (5) t cw (6) t bw
mosel vitelic V62C31162048 9 V62C31162048 rev. 0.3 february 1999 package diagrams 44-pin 400 mil tsop-ii 0.741[18.81] max 0.725 0.004 [18.41 0.10] 0.031 [0.80] 0.032 [0.80] 0.004 max 44 23 122 0.047 [1.20] max unit in inches [mm] 0.400 [10.16] 0.463 0.008 [11.76 0.20] 0.014 0.004 [0.35 0.10] 0.000 [0.0] min +0.004 -0.002 0 ? 0.020 0.006 [0.50 .019] 0.006 +0.01 -0.05 0.15
10 V62C31162048 rev. 0.3 february 1999 mosel vitelic V62C31162048 44-pin 400 mil soj (450 mil pin-to-pin) 1.131 +0.008 -0.014 28.73 +0.2 -0.36 0.008 +0.004 -0.002 0.20 0.033 [0.85] +0.10 -0.05 0.050 [1.27] 0.004 [0.10] 0.31 [0.8] min 0.102 [2.6] 0.091 [2.3 0.2] 0.138 0.008 [3.5 0.2] 0.005 [0.12] m 0.400 [10.16] 0.440 0.008 [11.18 0.20] 44 1 23 22 0.370 0.008 [9.4 0.20] unit in inches [mm] 0.029 [0.74] 0.016 +0.004 ?.005 0.041 [1.03 0.15] [0.40 0.10] +.006 ?007 +.008 ?007
mosel vitelic V62C31162048 11 V62C31162048 rev. 0.3 february 1999
mosel vitelic worldwide offices V62C31162048 ?copyright 1998, mosel vitelic inc. 2/99 printed in u.s.a. mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 011-852-665-4883 fax: 011-852-664-7535 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 011-886-2-545-1213 fax: 011-886-2-545-1209 1 creation road i science based ind. park hsin chu, taiwan, r.o.c. phone: 011-886-35-783344 fax: 011-886-35-792838 japan wbg marine west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-71 phone: 011-81-43-299-6000 fax: 011-81-43-299-6555 ireland & uk block a unit 2 broomfield business park malahide co. dublin, ireland phone: +353 1 8038020 fax: +353 1 8038049 germany (continental europe & israel ) 71083 herrenberg benzstr. 32 germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 562-498-3314 fax: 562-597-2174 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341 u.s. sales offices

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